Dr. Vibhuti Chauhan
Assistant Professor
Google Scholar: https://scholar.google.com/citations?user=231OjdUAAAAJ&hl=en&oi=ao
Scopus: https://www.scopus.com/authid/detail.uri?authorId=57226287756
ORCID: https://orcid.org/0000-0003-4954-1214
Vidwan: https://vidwan.inflibnet.ac.in/profile/581313
|
U.G |
Electronic Devices and Circuits |
|
Linear Integrated Circuits |
|
|
Design of Analog IC |
|
|
P.G |
Low Power VLSI Design |
|
Organization |
Start Date |
End Date |
Designation |
Nature of Work |
|
MANIT Bhopal |
07/11/2024 |
ongoing |
Assistant Professor (Grade-II) |
Teaching and Research |
| Bennett University | 23/06/2024 | 25/10/2024 | Assistant Professor | Teaching |
|
Name of the Student |
Topic |
Year of Award |
Co-Supervisor (if any) |
|
Umesh Choubey |
Thin Film Transistors |
- |
- |
| Dhanveer Singh Meena | Wide-bandgap MOS devices | - |
- |
| Chandra Prabhat | High-Performance MOS applications | - |
- |
|
Title |
Sponsoring Agency |
Duration |
Amount |
Co-PI (if any) |
|
Title |
Sponsoring Agency |
Duration |
Amount |
Co-Investigator (if any) |
|
Authors |
Title |
Journal |
VOL. NO., PAGE NO |
YEAR |
SCI/ Scopus |
IMPACT FACTOR |
| Abhay Pratap Singh, Vibhuti Chauhan, RK Baghel, Sukeshni Tirkey | Enhancing VLSI Design Efficiency With ML‐Based C‐ANN: Performance Optimization of Gate‐Stacked Ferroelectric FE‐MOSFETs for High‐Speed and RF Applications | International Journal of Numerical Modelling: Electronic Networks, Devices and Fields | 38 | 2025 | Both | 1.7 |
|
Vibhuti Chauhan, Dip Prakash Samajdar |
Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives |
Silicon Springer |
16 (3055–3062) |
2024 |
Both |
2.8 |
|
Vibhuti Chauhan, Dip Prakash Samajdar |
Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation |
Journal of Physics D: Applied Physics |
56 |
2023 |
Both |
3.1 |
|
Vibhuti Chauhan, Dip Prakash Samajdar |
Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET |
Semiconductor Science and Technology |
38 |
2023 |
Both |
1.9 |
|
Vibhuti Chauhan, Dip Prakash Samajdar, Navjeet Bagga |
Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET |
Silicon Springer |
15 (243-249) |
2022 |
Both |
2.8 |
|
Vibhuti Chauhan, Dip Prakash Samajdar, Navjeet Bagga |
Quasi-analytical model of surface potential and drain current for trigate negative capacitance FinFET: a superposition approach |
Semiconductor Science and Technology |
37 |
2022 |
Both |
1.9 |
|
Vibhuti Chauhan, Dip Prakash Samajdar, Navjeet Bagga |
Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET |
IEEE Transactions on Electron Devices |
69 (4717-4724) |
2022 |
Both |
3.1 |
|
Ankit Dixit, Dip Prakash Samajdar, Vibhuti Chauhan |
Sensitivity analysis of a novel negative capacitance FinFET for label-free biosensing |
IEEE Transactions on Electron Devices |
68 (5204-5210) |
2021 |
Both |
3.1 |
|
Vibhuti Chauhan, Dip Prakash Samajdar, Navjeet Bagga, Ankit Dixit |
A novel negative capacitance FinFET with ferroelectric spacer: proposal and investigation |
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control |
68 (3654-3657) |
2021 |
Both |
3.6 |
|
Vibhuti Chauhan, Dip Prakash Samajdar |
Recent advances in negative capacitance FinFETs for low power applications: a review |
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control |
68 (3056-3068) |
2021 |
Both |
3.6 |
|
Title |
Year |
Agency |
Co-Investigator(if any) |
Published/Granted |
|
A Tri-Gate Negative Capacitance FinFET device with Buried Interfacial Oxide layer and its Fabrication Method |
2023 | Government of India | Dr. Dip Prakash Samajdar | Granted |
