Organization

Start Date

End Date

Designation

Nature of Work

Maulana Azad National Institute of Technology, Bhopal.

Maulana Azad National Institute of Technology, Bhopal.

Maulana Azad National Institute of Technology, Bhopal.

Maulana Azad National Institute of Technology, Bhopal.

Name of the Student

Topic

Year of Award

Co-Supervisor (if any)

SunandaManke

Design of Trans-Receiver Circuit to Improve VCAT Performance in Next Generation SDH systems using VLSI

2010

Dr SD sapre

Vikas Gupta

Efficient VLSI Design and Implementation of Digital Controllers

2011

Dr RP Singh

JyotiDeshmukh

Integrating DBB with SVL: A technique for Leakage Power Reduction in CMOS Circuits

2012

MinalSaxena

Design and analysis of Timing and frequency Offset estimation Algorithm in VHDL

2012

SupriyaAggarwal

Design of efficient CORDIC Algorithm using generalized micro rotation selection for Digital Signal processing application

2013

Tarun Gupta

Design Of Power Efficient Footerless Domino Logic Nano Technology Circuits

2014

Anita Jain

Design Of Efficient 3D CORDIC Algorithm

2014

BhavanaSoni

Designof  Improved Routers for Network on Chip

2014

Arun K. Sunaniya

Design of Flash ADCs Using Submicron Power Dissipation reduction techniques.

2014

Archana Sharma

Design and analysis of Dielectric Resonator Antenna For Microwave Applications.

2014

Dr SC S

Rakhi Thakur

Improved Frame Detection and Timing Synchronization Model for OFDM system using Verilog

2015

UdayPanwar

Gate Replacement Technique for Reducing Worst Leakage Current in DSM Circuits

2015

Ajay K Dadoriya

Design And Analysis Of Low Power FinFET Circuits

2018

AfreenKhursheed

Efficient circuit modeling of CNT and GNR based integrated ON-CHIP interconnects with Buffers.

2018

Dr. Fozia H

Jaya Koshta

Improved VLSI architecture for variable block size Motion Estimation using SAD in HEVC

2021

VivekTiwari

Efficient Design and Implementation Of NOC Router Architecture

2021

Divya Gautam

Design and Implementation of Efficient Digital Filters

Cont.

Dr Bhavana P S

ZainabAizaz

Area And Energy Efficient Truncated Approximate  Carry-Based Booth Multipliers For Error Resilient Applications

Cont.

Shreya Gupta

VLSI Design (Topic ot finalized)

Cont.

Title

Sponsoring Agency

Duration

Amount

Co-PI (if any)

Modernization of Micromillimeter Antenna Lab

Title

Sponsoring Agency

Duration

Amount

Co-Investigator                       (if any)

Third party Inspection

Heavens techno system

1 year

Rs 260555

Dr. D K raghuwanshi

Dr R N Yadav

Pre delivery Inspection

DPI Bhopal

1 year

Rs 472000

Dr. D K raghuwanshi

Approaval of design…….SCADAsysrem

Indian Hume Pipe

Rs 75250

Dr Tarun KGupta

Approaval of design…….SCADAsysrem

JM vaghasiya(Nilkanth Coorporation

Rs 29500

Dr Tarun KGupta

Title of Paper

Approximate row-merging-based multipliers for Neural Network acceleration on FPGAs

Z Aizaz, K Khare, A Tirmizi 

SCI

IEEE Embedded Systems Letters, 2023

ASMPEC: Approximate-Sum based Mapping of Partial Products with Error Correction for Softcore multipliers on FPGAs

Z. Aizaz and K. Khare

in IEEE Transactions on Circuits and Systems II: Express Briefs

doi: 10.1109/TCSII.2023.3292947

Automation of optimal metal density filling for deep sub micron technology designs,

Afreen Khursheed, Fozia Z. Haque

scopus

Materials Today: Proceedings, ISSN 2214-7853,

https://doi.org/10.1016/j.matpr.2022.08.050 Sept. 2022,

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error

Z Aizaz, K Khare -

SCI

International Journal of Circuit Theory and Applications, 2022WILEY

1-19. doi:10.1002/cta.3252

Area and Power efficient Truncated Booth Multipliers using Approximate Carry based Error Compensation

ZainabAizaz

SCI

IEEE Transactions on Circuits and Systems--II: Express Briefs

Pp 1-5Digital Object Identifier: 10.1109/TCSII.2021.3094910

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique

DivyaGautam,Bhavana P Shrivastava

SCI

IEEE Access

vol. 9, pp. 44436-44441, 2021, doi: 10.1109/ACCESS.2021.3066292. 17/3/21

Optimized buffer insertion for efficient interconnects

designs

AfreenKhursheed,

SCI

International  Journal of Numerical Modeling  El. 2020;e2748. wileyonlinelibrary.com/journal/jnm © 2020 Accepted: 13 March 2020

John Wiley & Sons, Ltd pp 1-8

https://doi.org/10.1002/jnm.2748

Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects

AfreenKhursheed,

SCI

Journal Circuit World Publisher

Emerald Publishing Limited

Vol. 46 No. 2, pp. 71-83. https://doi.org/10.1108/CW-06-2019-0060 2020/1/13

An Efficient 4X4 Mesh Structure with a Combination of Two NoC Router Architecture

VivekTiwari*, SmitaShandilya.

Scopus

Journal Name: International Journal of Sensors, Wireless Communications and Control

DOI : 10.2174/2210327910666200306132045

Efficient Configurable Crossbar Switch Design For Noc

VivekTiwari

Scopus

INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH

VOLUME 8, ISSUE 11, NOVEMBER 2019 ISSN 2277-8616

Pp959-964

Design Of Speed & Area Efficient NoC

Architecture By Integrating Switches With

Simplified Decoder And Reduced Buffers

VivekTiwari

Scopus

INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH

VOLUME 8, ISSUE 10, pp2990-2994OCTOBER 2019 ISSN 2277-8616

Efficient Comparator Design for Motion

Estimation on FPGA

Jaya Koshta

Scopus

International Journal of Recent Technology and Engineering (IJRTE)

ISSN: 2277-3878, Volume-8 Issue-2, July 2019

High Speed Parallel SAD Architecture

Implementation on FPGA for HEVC encoder

Jaya Koshta

Scopus

International Journal of Engineering and Advanced Technology (IJEAT)

ISSN: 2249 – 8958, Volume-8 Issue-6, August 2019

Design and Analysis of Low‑Power Adiabatic Logic Circuits by Using CNTFET

Ajay Dadoriya

SCI

Circuits, Systems, and Signal Processinghttps://doi.org/10.1007/s00034-019-01059-41 February 2019

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Designing of ultra low power high speed repeaters for performance optimization of VLSI interconnects at 32nm.

Afreenkhursheed

SCI

International Journal of Numerical Modelling: Electronic Networks, Devices and Fieldshttp://dx.doi.org/10.1002/jnm.2516

2019/3

Volume32,Issue2,Pagese2516

Designing high-performance thermally stable repeaters for nano-interconnects

A Khursheed FZ Haque 

SCI

Journal of Computational Electronics,PublisherSpringer US

2019/3/15

Volume18, Issue1, Pages53-64

FDSOI-Based Area and Power-Efficient Robust Negative Charge Pump for Localized Body Bias Generator

A Jain, K Khare, AK Tripathi -

SCI

National Academy Science LettersPublisherSpringer India

Natl. Acad. Sci. Lett. 42, 345–349 (2019). https://doi.org/10.1007/s40009-018-0752-9pp1-5

Performance Tuning of Very Large Scale Integration Interconnects Integrated with Deep Sub Micron Repeaters

Afreenkhursheed

SCI

Journal of Nanoelectronics and Optoelectronics

Publisher :American Scientific Publishers

2018/12/12

Vol. 13, Issue12

pp1797-1806

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

Ajay Dadoriya

SCI

Microsystem Technologies

Volume24Issue8

pp3341-3348

Publisher

Springer Berlin Heidelberg2018/8/1

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits.

Ajay Dadoriya

SCIE

Int J Numer Model. 2018;

e2344. https://doi.org/10.1002/ jnm.2344

Volume31, Issue5

September/October 2018e2344

New Leakage Reduction Techniques for FinFET Technology with its Applications

Ajay Dadoriya

SCIE

JCSC

JCSC Vol. 27, No. 7 (June 2018). 

Integrating Sleep and Pass Transistor Logic For Leakage Power Reduction in FinFET Circuits

Ajay Dadoriya

SCIE

Journal of Computational Electronics (JCEL)Springer  SCIE

 Volume 16, Issue 3, September 2017pp 867–874

Nanoscale: Low Power, Noise Tolerant Wide Fan-in Domino FinFET OR Logic

Ajay Dadoriya

SCIE

Journal of Nanoelectronics and Optoelectronics (American Scientific Publishers) SCIE

Volume 13, Number 4, April 2018, pp. 562-571(10)2018/4/1

Ultra Low Power FinFET Based Domino Circuits

Ajay Dadoriya

SCI

International Journal of  Electronics Taylor &francisSCI

Volume 104, Issue6 Jan2017pp 952-967

Leakage Reduction by using FinFET Technique for Nanoscale Technology Circuits

Ajay Dadoriya

SCIE

Journal of Nanoelectronics and Optoelectronics (American Scientific Publishers) SCIE

Vol. 11, pp. 1–8, 2016

Ultra Low Power High Speed Domino
Logic Circuit By Using Finfet Technology

Ajay Dadoriya

Scopus

AEEE Advances In Electrical And Electronic Engineering

Vol: 14, No:1, pp.66-74 March. 2016.

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

UdayPanwar

SCI

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Volume 29, Issue 4 July/August 2016 Pages 565–576

Concept, Design, and Implementation of Reconfigurable CORDIC

SupriyaAggarwal

SCI

IEEE Transactions on VLSI Systems

1063-8210 © 2015 IEEE

A Survey on Nano-Scale Double Gate CMOS Transistor

Ajay Dadoriya

Scopus

Advanced Science Letters, American Scientific Publishers

Vol. 21, No. 9, Sept.2015, pp. 2830-2832(3)

Lector with Footed Diode Inverter:A technique for Leakage Reduction in Domono Circuits

Tarun Gupta

SCIE

Circuit Systems Signal ProcessingSPRINGER ISSN No.0278-081X (IF-0.98)

Doi:10.1007/s00034-013-9615-2

CORDIC based Window Implementation to Minimize Area and Pipeline Depth

SupriyaAggarwal

SCI

IET Signal Processing, ISSN751-9675( IF 2011 – 0.56)

Published on line doi: 10.1049/iet-spr.2012.0021

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

SupriyaAggarwal

SCI

International Journal of Reconfigurable Computing,Hindawi Publishing Corporation ISSN: 1687-7195

Volume 2012Article ID 185784, 8 pages  doi:10.1155/2012/185784

Dynamic SVL for Low Leakage Power and High Performance in CMOS Digital Circuits

JyotiDeshmukh

SCI

International Journal of Electronics, Taylor & Francis ISSN 0020-7217

( IF 2011 – 0.440)

Jul 2012,Vol. 99, No. 12, pp. 1717-1728,

Simulation and analysis of Power Switches for Low Standby power in CMOS VLSI Design

JyotiDeshmukh

AMSE Journal Modelling A, ISSN No. 0761-2494

Vol. 85, nº2, 2012, pp 35-46

Scale-Free Hyperbolic CORDIC Processor and its Application to Waveform Generation

SupriyaAggarwal et. al.

SCI

IEEE Trans. of Circuits and Systems I ISSN 1549-8328 (IF 1.97)

Vol. 60, No. 2, 314-326, Feb 2013

Low Complexity VLSI Implementation of CORDIC based Exponent Calculation for Neural Networks

SupriyaAggarwal

SCI

International Journal of Electronics, Taylor & Francis ISSN 0020-7217( IF 2011 – 0.440)

Nov. 2012,Vol. 99, No. 11, pp. 1471-1488

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence

SupriyaAggarwal

SCIE

The Journal of Signal Processing Systems, Springer ISSN 1939-8018 (IF 2011 – 0.672)

Volume 70 Issue 1, January 2013 Pages 49-57 

Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm

SupriyaAggarwal

SCI

The Computer Journal, Oxford Publications ISSN 1460-2067 (IF 2011 – 0.785)

Vol. 55 No. 5 May 2012, pp. 616-628

Area-Time Efficient Scaling-Free CORDIC using generalized Micro-rotation Selection

SupriyaAggarwal et. al.

SCI

IEEE Transactions on VLSI Systems ISSN 1063-8210 (IF 1.219)

Vol.20 No.8 Aug 2012,pp 1542-1546

FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems

SunandaManke et.al.

SCIE

International Journal of Signal Processing Systems. ISSN 1939-8018 (IF 2011 – 0.672)

Volume 67 Number 2 (May 2012) pp105–116

VCAT Synchronizer -Reduction of Buffer Size in Next Generation SDH Networks

SunandaManke et.al.

SCI

European Transactions on Telecommunications ISSN 1124-318X (IF 0.454)

Sept 2011;  vol22: pp 500–514

FPGA Implementation of Area-Time Efficient CORDIC Processor dedicated to compute exponentials in Neural Networks

SupriyaAggarwal

ESCI, Scopus

International Journal of Signal and Imaging Systems Engineering IJSISE,Inderscience pub. Switzerland. ISSN 1748-0698

Vol. 3 No. 4, 2010, pp. 255-260

Synthesis and Simulation of VDOS (Voice and data over SDH) transmitter-VHDL approach

SunandaManke et.al.

Scopus

AMSE International Journal of Signal Processing and Pattern Recognition, France. ISSN No. 0761-2494)

2009 B Vol. 52 No. 1-2, pp. 72-83

Modeling And Simulation Of A Efficient Low Bit Rate Speech technique using MATLAB

NilayKhare

Scopus

International  Journal of ASME, France "best year book" of 2005;

2005, pp 33-42

Design and evaluation of Huffman encoder for speech and image data compression in FPGA

NilayKhare

Scopus

International journal of Management and Systems, Australia

Vol. 22 No.1, Jan-April 2006,Pp 45-52

FPGA Implementation of Pipelined Multifunction unit for FP arithmetic operations

NilayKhare

Scopus

International  Journal of AMSE, France

Vol 12n1, Advance D 2007, pp53-64

Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder

SCI

Journal of CSIR, NISCAIRISSN 0022-4456  IF-0.56

Published Vol64,May 2005,pp354-357

Comparison of Pipelined IEEE-754 Standard FP multiplier with Unpipelined Multiplier

SCI

Journal of CSIR, NISCAIR ISSN 0022-4456  IF-0.56

Vol. 65, Nov.2006,pp: 900-904

Title

Year

Agency

Co-Investigator(if any)

Published/Granted

Granted

 A Smart Agriculture System And Method Integrated With Iot Devices

2020

IPR

Nilay Khare Et Al

Granted

A Method For Prediction Of Covid-19 Based On Machine Learning Algorithm

2022

AU

Afreen Khursheed Et Al.

Published